VLSI Concepts is interested in Electrical and IC CAD products which run under the Linux environment.
Development has begun on a Schematic and IC Layout Editor (IC) which runs in this environment.
Both are written using ANSI standard C to implement the underlying database and important algorithms.
Other algorithms and the user interface are implemented using Tcl and Tk.  An augmented Tcl interpretter is included to permit the user to create procedures and scripts to further customize and automate the design process.

The layout editor can operate as a standard "polygon-pusher", but also can use device generators to
create more complex primitives such as transistors, contacts, etc.   Basic device generators are provided
and the user can customize them or add additional types.

Tcl functions have been provided to allow a user to manipulate the underlying database via procedures.   This permits the user to create complex structures in code, eliminating hours of tedious graphical interaction
at the polygon level.

Currently, IC (the editor) is a proprietary tool running under Redhat Linux.   Let us know if this looks like a tool you would want to purchase and features/options that would be of interest to you.  We would also be interested in hearing what other IC/ECAD tools you would like to see in the Linux environment.
Mail your comments and questions to: hepler@vlsi-concepts.com

Here are a couple of screen shots from the Linux version of IC:

This is the entry point to IC:

This screen shows a couple of bipolar devices generated automatically by device generators.  Each of the two devices shown below are objects that can be manipulated as primitives:


 

This screen shows a view of the schematic editor.  Basic generic symbols can be produced by selecting the function from the buttons on the left column and filling in the appropriate choices from the popup form that appears.  For example, the two rectangles below represent 16-bit DFF (registers) with synchronous, low-active reset.   The purple diamond shapes represent ports which are not yet connected.

A finished schematic can be saved as a structural VHDL netlist.  Generic driven VHDL models are available for the symbols: